The invention relates generally to dynamic random access memory (DRAM) devices and, more specifically, to a device and method capable of converting a full density memory device to a reduced density memory device, thereby compensating for cell failures in a plurality of cell blocks.
DRAM integrated circuits (ICs) are formed from complimentary metal oxide semiconductors (CMOS) circuits. A DRAM device typically includes millions or billions of individual DRAM memory cells arranged in an array, with each cell storing information in the form of one bit (i.e., a logic 1 or a logic 0) of data. The memory cells are arranged in a matrix of addressable rows and columns, with each row corresponding to a cell block containing a multi-bit word of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. The bit of data in each cell is stored on the capacitor as a charge, or lack thereof. This data must be refreshed because the charge of the capacitor leaks therefrom over time (i.e., over the charge, or data retention time of the cell). In order to prevent the loss of data, the data storage in the cell must be refreshed before the end of the data retention time.
One problem with conventional high density DRAMs results during a wafer production when many individual memory cells are identified as being defective due to, for example, a shortened memory cell capacitor or an improper electrical connection within the memory cell. DRAM wafers are tested after fabrication to identify defective memory cells. The defective cells are incapable of having data or information stored to or read from that location. It is important to identify defective memory cells prior to programming the DRAM so that no data bits will be stored or attempted to be stored at these locations. Access to a defective memory cell must be redirected to a different memory cell, so that data will be accurately stored within the DRAM.
One solution to the problem of defective cell blocks incorporating defective memory cells adopted by the industry includes utilizing a redundant scheme within a DRAM. The redundant scheme including redundant rows and columns of memory cells to replace the defective memory cells. However, a substantial amount of additional circuitry must be provided to redirect memory access to redundant memory cells. This additional circuitry may be expensive and reduce the overall profitability of the circuitry.
Another approach to solving the defective memory cell problem includes coupling two memory cells in respective rows to the same digit line or different digit lines for a specific column. For example, the memory cell in an even row is coupled to a digit line and the memory cell in an odd row is coupled to a complimentary digit line. If one of the memory cells is defective, the charged from the non-defective memory cell can charge the voltage on the digit line to be detected by the sense amplifier. However, solution permits storage of data into memory cells by initially reducing the capacity of a memory array to 50 percent. In addition, if both of the corresponding memory cells are defective, the data stored in those memory cells will be lost and the reliability of the DRAM will be compromised.
In some instances, a particular DRAM is not repairable with the redundant row and column scheme due to a large number of defective memory cells within various rows or cell blocks. The most widely used solution in the industry to the problem of too many defective memory cells is the conventional approach of converting a full density memory device to a perfect half memory density device. This conventional solution is inflexible in that it simply recognizes a defective cell block having defective memory cells and essentially reduces each bank of memory by 50 percent. Assuming a 256 mega bit memory device, each bank having 64 mega bit density and each bank consisting of 16 cell blocks, this solution utilizes either the top half portion of a bank from cell block 0 to cell block 7 or the bottom half portion of the bank from cell block 8 to cell block 15.
This conventional half density option has severe limitations in converting an irreparable full density memory device to a perfect half density memory device. For example, in the situation in which any one of the cell blocks between cell block 0 to cell block 7 of a particularly bank has cell failures and any one of the cell blocks between cell block 8 to cell block 15 of the same bank has memory cell failures, the half density conversion fails for that bank. The perfect half density option is incapable of providing an alternate location for all defective cells. Neither the top half portion nor the bottom half portion can be utilized and information cannot be stored anywhere within the particular bank. This solution is inflexible in that it cannot accommodate cell failures on opposite halves (top half and bottom half) of the bank.